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preliminary this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 20380 rev: b amendment/ 0 issue date: april 1997 5.0 v-only flash am29f400at/am29f400ab 4 megabit (524,288 x 8-bit/262,144 x 16-bit) cmos 5.0 volt-only, sector erase flash memory distinctive characteristics n 5.0 v 10% for read and write operations minimizes system level power requirements n compatible with jedec-standards pinout and software compatible with single-power-supply ?sh superior inadvertent write protection n package options 44-pin so 48-pin tsop n minimum 100,000 write/erase cycles guaranteed n high performance 60 ns maximum access time n sector erase architecture one 16 kbyte, two 8 kbytes, one 32 kbyte, and seven 64 kbytes any combination of sectors can be erased. also supports full chip erase. n sector protection hardware method that disables any combination of sectors from write or erase operations. implemented using standard prom programming equipment. n embedded erase ? algorithms automatically preprograms and erases the chip or any sector n embedded program ? algorithms automatically programs and veri?s data at speci?d address n data polling and toggle bit feature for detection of program or erase cycle completion n ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion n erase suspend/resume supports reading data from a sector not being erased n low power consumption 20 ma typical active read current for byte mode 28 ma typical active read current for word mode 30 ma typical program/erase current n enhanced power management for standby mode ? m a typical standby current n boot code sector architecture t = top sector b = bottom sector n hardware reset pin resets internal state machine to the read mode general description the am29f400a is a 4 mbit, 5.0 volt-only flash memory organized as 512 kbytes of 8 bits each or 256 kwords of 16 bits each. the 4 mbits of data is divided into 11 sectors of one 16 kbyte, two 8 kbyte, one 32 kbyte, and seven 64 kbytes, for ?xible erase capability. the 8 bits of data will appear on dq0?q7 or 16 bits on dq0?q15. the am29f400a is offered in 44-pin so and 48-pin tsop packages. this device is designed to be programmed in-system with the standard system 5.0 volt v cc supply. 12.0 volt v pp is not required for program or erase operations. the device can also be re- programmed in standard eprom programmers. the standard am29f400a offers access times of 60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has sepa- rate chip enable (ce ), write enable (we ) and output enable (oe ) controls. the am29f400a is entirely command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write timings. register con- tents serve as input to an internal state-machine which controls the erase and programming circuitry.
2 am29f400at/am29f400ab preliminary write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0 volt flash or eprom devices. the am29f400a is programmed by executing the pro- gram command sequence. this will invoke the embed- ded program algorithm which is an internal algorithm that automatically times the program pulse widths and veri?s proper cell margin. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automat- ically times the erase pulse widths and veri?s proper cell margin. this device also features a sector erase architecture. this allows for sectors of memory to be erased and re- programmed without affecting the data contents of other sectors. a sector is typically erased and veri?d within 1.5 seconds. the am29f400a is erased when shipped from the factory. the am29f400a device also features hardware sector protection. this feature will disable both program and erase operations in any combination of eleven sectors of memory. amd has implemented an erase suspend feature that enables the user to put erase on hold for any period of time to read data from a sector that was not being erased. thus, true background erase can be achieved. the device features single 5.0 volt power supply oper- ation for both read and write functions. internally gen- erated and regulated voltages are provided for the program and erase operations. a low v cc detector au- tomatically inhibits write operations during power tran- sitions. the end of program or erase is detected by the ry/by pin. data polling of dq7, or by the toggle bit (dq6). once the end of a program or erase cycle has been completed, the device automatically resets to the read mode. the am29f400a also has a hardware reset pin. when this pin is driven low, execution of any embed- ded program algorithm or embedded erase algorithm will be terminated. the internal state machine will then be reset into the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device will be auto- matically reset to the read mode and will have errone- ous data stored in the address locations being operated on. these locations will need rewriting after the reset. resetting the device will enable the sys- tems microprocessor to read the boot-up ?mware from the flash memory. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the am29f400a memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are pro- grammed one byte/word at a time using the eprom programming mechanism of hot electron injection. flexible sector-erase architecture n one 16 kbyte, two 8 kbytes, one 32 kbyte, and seven 64 kbyte sectors n individual-sector or multiple-sector erase capability n sector protection is user de?able am29f400at sector architecture am29f400ab sector architecture 16 kbyte 8 kbyte 8 kbyte 32 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 20380b-1 7ffffh 3ffffh 7bfffh 3dfffh 79fffh 3cfffh 77fffh 3bfffh 6ffffh 37fffh 5ffffh 2ffffh 4ffffh 27fffh 3ffffh 1ffffh 2ffffh 17fffh 1ffffh 0ffffh 0ffffh 07fffh 00000h 00000h (x8) (x16) 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte 8 kbyte 8 kbyte 16 kbyte sa10 sa9 sa8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 20380b-2 7ffffh 3ffffh 6bfffh 37fffh 5ffffh 2ffffh 4ffffh 27fffh 3ffffh 1ffffh 2ffffh 17fffh 1ffffh 0ffffh 0ffffh 07fffh 07fffh 03fffh 05fffh 02fffh 03fffh 01fffh 00000h 00000h (x8) (x16)
am29f400at/am29f400ab 3 preliminary 5.0 v-only flash product selector guide block diagram family part no: am29f400a ordering part no:v cc = 5.0 v 5 % -65 v cc = 5.0 v 10% -70 -90 -120 -150 max access time (ns) 60 70 90 120 150 ce (e ) access (ns) 60 70 90 120 150 oe (g ) access (ns) 30 30 35 50 55 erase voltage generator input/output buffers data latch y-gating cell matrix x-decoder y-decoder address latch chip enable output enable logic pgm voltage generator timer v cc detector state control command register we ce oe a0-a17 stb stb dq0?q15 ry/by buffer ry/by byte reset a-1 v cc v ss 20380b-3
4 am29f400at/am29f400ab preliminary connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 so 20380b-4 nc ry/by a17 a7 a6 a5 a4 a3 a2 a1 a0 ce v ss oe dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 reset we a8 a9 a10 a11 a12 a13 a14 a15 a16 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
am29f400at/am29f400ab 5 preliminary 5.0 v-only flash connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 a16 dq2 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe v ss ce a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 nc a14 a13 a12 a11 a10 a9 a8 nc nc we reset nc nc ry/ by a1 a17 a7 a6 a5 a4 a3 a2 standard tsop 20380b-5 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a16 dq2 byte v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe v ss ce a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 a15 nc a14 a13 a12 a11 a10 a9 a8 nc nc we reset nc nc ry/ by a1 a17 a7 a6 a5 a4 a3 a2 reverse tsop 20380b-6
6 am29f400at/am29f400ab preliminary pin configuration a1, a0?17 = 18 addresses byte = selects 8-bit or 16-bit mode ce = chip enable dq0?q15 = 16 data inputs/outputs nc = pin not connected internally oe = output enable reset = hardware reset pin, active low ry/by = ready/busy output v ss = +5.0 volt single-power supply ( 10% for -90, -120, -150) or ( 5% for -75) v ss = device ground we = write enable logic symbol 18 16 or 8 dq0?q15 a0?17 ce (e ) oe (g ) we (w ) a-1 ry/by reset byte 20380b-7
am29f400at/am29f400ab 7 preliminary 5.0 v-only flash ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the following: valid combinations valid combinations list con?urations planned to be sup- ported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. temperature range c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package type e = 48-pin thin small outline package (tsop) standard pinout (ts 048) f = 48-pin thin small outline package (tsop) reverse pinout (tsr048) s = 44-pin small outline package (so 044) device number/description am29f400a 4 megabit (512k x 8-bit/256k x 16-bit) cmos flash memory 5.0 volt-only program and erase am29f400a -65 e c optional processing blank = standard processing b = burn-in b speed option see product selector guide and valid combinations t boot code sector architecture t = top sector b = bottom sector valid combinations am29f400at/b-65 ec, ei, fc, fi, sc, si am29f400at/b-70 ec, ei, ee, eeb, fc, fi, fe, feb, sc, si, se, seb am29f400at/b-90 am29f400at/b-120 am29f400at/b-150
8 am29f400at/am29f400ab preliminary table 1. am29f400a user bus operations (byte = v ih ) table 2. am29f400a user bus operations (byte = v il ) legend: l = logic 0, h = logic 1, x = don? care. see characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 4. 2. refer to the section on sector protection. read mode the am29f400a has two control functions which must be satis?d in order to obtain data at the outputs. ce is the power control and should be used for device selec- tion. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (as- suming the addresses have been stable for at least t acc -t oe time). standby mode there are two ways to implement the standby mode on the am29f400a device, both using the ce pin. a cmos standby mode is achieved with the ce input held at v cc 0.5 v. under this condition the current is typically reduced to less than 5 m a. a ttl standby mode is achieved with the ce pin held at v ih . under this condition the current is typically reduced to 1 ma. in the standby mode the outputs are in the high imped- ance state, independent of the oe input. operation ce oe we a0 a1 a6 a9 dq0?q15 reset autoselect, amd manuf. code (note 1) l l h l l l v id code h autoselect device code (note 1) l l h h l l v id code h read l l h a0 a1 a6 a9 d out h standby h xxxxxx high z h output disable l h h xxxx high z h write l h l a0 a1 a6 a9 d in h verify sector protect (note 2) l lhlhlv id code h temporary sector unprotect xxxxxxx x v id hardware reset xxxxxxx high z l operation ce oe we a0 a1 a6 a9 dq0?q7 dq8?q15 reset autoselect, amd manuf. code (note 1) llhlllv id code high z h autoselect device code (note 1) l l h h l l v id code high z h read l l h a0 a1 a6 a9 d out high z h standby h xxxxxx high z high z h output disable l h h xxxx high z high z h write l h l a0 a1 a6 a9 d in high z h verify sector protect (note 2) l lhlhlv id code high z h temporary sector unprotect xxxxxxx x high z v id hardware reset xxxxxxx high z high z l
am29f400at/am29f400ab 9 preliminary 5.0 v-only flash output disable with the oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading of a binary code from the device and will identify its manufacturer and type. this mode is intended for use by program- ming equipment for the purpose of automatically matching the device to be programmed with its corre- sponding programming algorithm. this mode is func- tional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a9. two identi?r bytes may then be sequenced from the device outputs by toggling address a0 from v il to v ih . all addresses are don? cares except a0, a1, and a6 (see table 3). the manufacturer and device codes may also be read via the command register, for instances when the am29f400a is erased or programmed in a system without access to high voltage on the a9 pin. the com- mand sequence is illustrated in table 4 (see autoselect command sequence). byte 0 (a0 = v il ) represents the manufacturers code (amd=01h) and byte 1 (a0 = v ih ) the device identi?r code (am29f400at = 23h and am29f400ab = abh for x8 mode; am29f400at = 2223h and am29f400ab = 22abh for x16 mode). these two bytes/words are given in the table below. all identi?rs for manufacturer and device will exhibit odd parity with dq7 de?ed as the parity bit. in order to read the proper device codes when executing the autoselect, a1 must be v il (see tables 3 and 4). the autoselect mode also facilitates the determination of sector protection in the system. by performing a read operation at the address location xx02h with the higher order address bits a12?17 set to the desired sector address, the device will return 01h for a pro- tected sector and 00h for a non-protected sector. table 3. am29f400a sector protection verify autoselect codes *outputs 01h at protected sector addresses table 4. expanded autoselect code table b) - byte mode (w) - word mode type a12-a17 a6 a1 a0 code (hex) manufacturer code-amd x v il v il v il 01h am29f400a device am29f400at byte xv il v il v ih 23h word 2223h am29f400ab byte xv il v il v ih abh word 22abh sector protection sector address v il v ih v il 01h* type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturer code-amd 01h 00000000 00000001 am29f400a device am29f400at(b) (w) 23h 2223h a-1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 1 am29f400ab(b) (w) abh 22abh a-1 0 hi-z 0 hi-z 1 hi-z 0 hi-z 0 hi-z 0 hi-z 1 hi-z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 sector protection 01h 00000000 00000001
10 am29f400at/am29f400ab preliminary table 5. sector address tables (am29f400at) table 6. sector address tables (am29f400ab) write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state ma- chine outputs dictate the function of the device. the command register itself does not occupy any ad- dressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written to by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens ?st. standard microprocessor write timings are used. refer to ac write characteristics and the erase/pro- gramming waveforms for speci? timing parameters. sector protection the am29f400a features hardware sector protection. this feature will disable both program and erase opera- tions in any combination of ten sectors of memory. the sector protect feature is enabled using programming equipment at the users site. the device is shipped with all sectors unprotected. alternatively, amd may program and protect sectors in the factory prior to shipping the device (amds expressflash ? service). a17 a16 a15 a14 a13 a12 (x8) address range (x16) address range sa0 0 0 0 x x x 00000h-0ffffh 00000h-07fffh sa1 0 0 1 x x x 10000h-1ffffh 08000h-0ffffh sa2 0 1 0 x x x 20000h-2ffffh 10000h-17fffh sa3 0 1 1 x x x 30000h-3ffffh 18000h-1ffffh sa4 1 0 0 x x x 40000h-4ffffh 20000h-27fffh sa5 1 0 1 x x x 50000h-5ffffh 28000h-2ffffh sa6 1 1 0 x x x 60000h-6ffffh 30000h-37fffh sa71110xx 70000h-77fffh 38000h-3bfffh sa8111100 78000h-79fffh 3c000h-3cfffh sa9111101 7a000h-7bfffh 3d000h-3dfffh sa10 11111x 7c000h-7ffffh 3e000h-3ffffh a17 a16 a15 a14 a13 a12 (x8) address range (x16) address range sa000000x 00000h-03fffh 00000h-01fffh sa1000010 04000h-05fffh 02000h-02fffh sa2000011 06000h-07fffh 03000h-03fffh sa30001xx 08000h-0ffffh 04000h-07fffh sa4 0 0 1 x x x 10000h-1ffffh 08000h-0ffffh sa5 0 1 0 x x x 20000h-2ffffh 10000h-17fffh sa6 0 1 1 x x x 30000h-3ffffh 18000h-1ffffh sa7 1 0 0 x x x 40000h-4ffffh 20000h-27fffh sa8 1 0 1 x x x 50000h-5ffffh 28000h-2ffffh sa9 1 1 0 x x x 60000h-6ffffh 30000h-37fffh sa10 1 1 1 x x x 70000h-7ffffh 38000h-3ffffh
am29f400at/am29f400ab 11 preliminary 5.0 v-only flash it is possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order address bits a12?17 is the desired sector address, will produce a logical ? at dq0 for a protected sector. see table 3 for autoselect codes. temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors of the am29f400a device in order to change data in-system. the sector unprotect mode is activated by setting the reset pin to high volt- age (12v). during this mode, formerly protected sec- tors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. refer to figures 16 and 17. command de?itions device operations are selected by writing speci? ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode . table 7 de?es the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) com- mands are valid only while the sector erase operation is in progress. moreover, both reset/read commands are functionally equivalent, resetting the device to the read mode.
12 am29f400at/am29f400ab preliminary table 7. am29f400a command de?itions (notes 1?) notes: 1. bus operations are de?ed in tables 1 and 2. 2. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a17?12 will uniquely select any sector. 3. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we . 4. reading from non-erasing sectors is allowed in the erase suspend mode. 5. address bits a17?15 are don? care for unlock and command cycles. 6. the system should generate the following address patterns: word mode: 5555h or 2aaah to addresses a0?14 byte mode: aaaah or 5555h to addresses a-1?14. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/ reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value en- sures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the speci? timing parameters. command sequence read/reset bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data reset/read 1 xxxxh f0h reset/ read word 3 5555h aah 2aaah 55h 5555h f0h ra rd byte aaaah 5555h aaaah autoselect word 3 5555h aah 2aaah 55h 5555h 90h 01h 2223h (t device id) 22abh (b device id) byte aaaah 5555h aaaah 23h (t device id) abh (b device id) word /byte 00h 01h (t/b manuf. id) program word 4 5555h aah 2aaah 55h 5555h a0h pa pd byte aaaah 5555h aaaah chip erase word 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h byte aaaah 5555h aaaah aaaah 5555h aaaah sector erase word 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h byte aaaah 5555h aaaah aaaah 5555h erase suspend 1 xxxxh b0h erase resume 1 xxxxh 30h
am29f400at/am29f400ab 13 preliminary 5.0 v-only flash autoselect command flash memories are intended for use in applications where the local cpu can alter memory contents. as such, manufacture and device codes must be accessible while the device resides in the target system. prom programmers typically access the sig- nature codes by raising a9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally a desirable system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autose- lect command sequence into the command register. following the command write, a read cycle from ad- dress xx00h retrieves the manufacture code of 01h. a read cycle from address xx01h returns the device code (am29f400at = 23h and am29f400ab = abh for x8 mode; am29f400at = 2223h and am29f400ab = 22abh for x16 mode) (see tables 3 and 4). all manufacturer and device codes will exhibit odd par- ity with dq7 de?ed as the parity bit. furthermore, the write protect status of sectors can be read in this mode. scanning the sector addresses (a17, a16, a15, a14, a13, and a12) while (a6, a1, a0) = (0, 1, 0) will produce a logical ? at device output dq0 for a protected sector. to terminate the operation, it is necessary to write the read/reset command sequence into the register. byte/word programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two ?nlock write cycles. these are followed by the program setup command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever hap- pens ?st. the rising edge of ce or we (whichever hap- pens rst) begins programming using the embedded program algorithm. upon executing the algorithm, the system is not required to provide further controls or tim- ings. the device will automatically provide adequate in- ternally generated program pulses and verify the programmed cell margin. the automatic programming operation is completed when the data on dq7 (also used as data polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see table 8, write operation sta- tus). therefore, the device requires that a valid address to the device be supplied by the system at this particu- lar instance of time for data polling operations. data polling must be performed at the memory location which is being programmed. any commands written to the chip during the embed- ded program algorithm will be ignored. if a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. programming is allowed in any sequence and across sector boundaries. beware that a data ? cannot be programmed back to a ?? attempting to do so may cause the device to exceed programming time limits (dq5 = 1) or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still ?13? only erase operations can convert ?? to ??. figure 1 illustrates the embedded programming algo- rithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two ?nlock write cycles. these are followed by writing the ?etup command. two more ?nlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. the erase is performed sequentially on all sectors at the same time (see table ?rase and programming perfor- mance?. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and termi- nates when the data on dq7 is ? (see write operation status section) at which time the device returns to read the mode. figure 1 illustrates the embedded erase algorithm using typical command strings and bus operations. sector erase sector erase is a six bus cycle operation. there are two ?nlock write cycles. these are followed by writing the ?et-up command. two more ?nlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (30h) is latched on the rising edge of we . after a time-out of 100 m s from the rising edge of the last sector erase command, the sector erase op- eration will begin. multiple sectors may be erased sequentially by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be sequentially erased. the time between writes must be less than 100 m s otherwise that command will not be
14 am29f400at/am29f400ab preliminary accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 100 m s from the rising edge of the last we will initiate the execution of the sector erase command(s). if another falling edge of the we occurs within the 100 m s time-out window the timer is reset. (monitor dq3 to determine if the sector erase timer window is still open, see section dq3, sector erase timer.) any command other than sector erase or erase suspend during this period will reset the de- vice to the read mode, ignoring the previous command string. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for dq3, sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to10). sector erase does not require the user to program the device prior to erase. the device automatically pro- grams all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not af- fected. the system is not required to provide any con- trols or timings during these operations. the automatic sector erase begins after the 100 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq7, data polling, is ? (see write opera- tion status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. figure 1 illustrates the embedded erase algorithm using typical command strings and bus operations. erase suspend the erase suspend command allows the user to inter- rupt a sector erase operation and then perform data reads from a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written dur- ing the chip erase operation or embedded program algorithm. writing the erase suspend com- mand during the sector erase time-out results in imme- diate termination of the time-out period and suspension of the erase operation. any other command written during the erase suspend mode will be ignored except the erase resume command. writing the erase resume com- mand resumes the erase operation. the addresses are ?on?-cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a max- imum of 15 m s to suspend the erase operation. when the device has entered the erase-suspended mode, dq6 will stop toggling. the user must use the address of a sector being erased for reading dq6 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. an- other erase suspend command can be written after the chip has resumed erasing. write operation status table 8. write operation status notes: 1. d8?15 = don? care for x16 mode. 2. dq4 for amd internal use only. status dq7 dq6 dq5 dq3 in progress auto-programming dq7 toggle 0 0 program/erase in auto-erase 0 toggle 0 1 exceeded time limits auto-programming dq7 toggle 1 0 program/erase in auto-erase 0 toggle 1 1
am29f400at/am29f400ab 15 preliminary 5.0 v-only flash dq7 data polling the am29f400a device features data polling as a method to indicate to the host that the embedded algo- rithms are in progress or completed. during the embedded program algorithm an attempt to read the device will produce the complement of the data last written to dq7. upon completion of the embedded pro- gram algorithm, an attempt to read the device will pro- duce the true data last written to dq7. during the embedded erase algorithm, an attempt to read the device will produce a ? at the dq7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a ? at the dq7 output. the ?wchart for data polling (dq7) is shown in figure 2. for chip erase, the data polling is valid after the rising edge of the sixth we pulse in the six write pulse se- quence. for sector erase, the data polling is valid after the last rising edge of the sector erase we pulse. data polling must be performed at sector addresses within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. just prior to the completion of embedded algorithm operations dq7 may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the sys- tem samples the dq7 output, it may read the status or valid data. even if the device has completed the em- bedded algorithm operations and dq7 has a valid data, the data outputs on dq0?q6 may be still in- valid. the valid data on dq0?q7 will be read on the successive read attempts. the data polling feature is only active during the em- bedded programming algorithm, embedded erase al- gorithm, or sector erase time-out (see table 7). see figure 10 for the data polling timing speci?ations and diagrams. dq6 toggle bit the am29f400a also features the ?oggle bit as a method to indicate to the host system that the embed- ded algorithms are in progress or completed. during an embedded program or erase algorithm cy- cle, successive attempts to read (oe toggling) data from the device at any address will result in dq6 tog- gling between one and zero. once the embedded pro- gram or erase algorithm cycle is completed, dq6 will stop toggling and valid data will be read on the next successive attempt. during programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth we pulse in the six write pulse sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. the toggle bit is active during the sector time-out. either ce or oe toggling will cause dq6 to toggle. in addition, an erase suspend/resume command will cause dq6 to toggle. see figure 11 for the toggle bit timing speci?ations and diagrams. dq5 exceeded timing limits dq5 will indicate if the program or erase time has ex- ceeded the specied limits (internal pulse count). under these conditions dq5 will produce a ?? this is a failure condition which indicates that the program or erase cycle was not successfully completed. data poll- ing is the only operating function of the device under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output dis- able functions as described in table 1. the dq5 failure condition will also appear if a user tries to program a 1 to a location that is previously pro- grammed to 0. in this case the device locks out and never completes the embedded program algorithm. hence, the system never reads a valid data on dq7 bit and dq6 never stops toggling. once the device has ex- ceeded timing limits, the dq5 bit will indicate a ?. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset the device. dq3 sector erase timer after the completion of the initial sector erase com- mand sequence the sector erase time-out will begin. dq3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, dq3 may be used to determine if the sector erase timer window is still open. if dq3 is high (?? the internally controlled erase cycle has begun; attempts to write subsequent commands (other than erase suspend) to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if dq3 is low (??, the device will accept additional sector erase commands. to insure the command has been ac- cepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 were high on the second sta- tus check, the command may not have been accepted. refer to table 8: write operation status.
16 am29f400at/am29f400ab preliminary ry/by ready/busy the am29f400a provides a ry/by open-drain output pin as a way to indicate to the host system that the em- bedded algorithms are either in progress or have been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the device will not accept any additional program or erase com- mands with the exception of the erase suspend com- mand. if the am29f400a is placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin should be ignored while reset is at v il . refer to figure 12 for a detailed timing diagram. since this is an open-drain output, several ry/by pins can be tied together in parallel with a pull-up resistor to v cc . reset hardware reset the am29f400a device may be reset by driving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500 ns. any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional 50 ns before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be indeterminate. the reset pin may be tied to the system reset input. therefore, if a system reset occurs during the embed- ded program or erase algorithm, the device will be au- tomatically reset to read mode and this will enable the systems microprocessor to read the boot-up ?mware from the flash memory. byte/word con?uration the byte pin selects the byte (8-bit) mode or word (16 bit) mode for the am29f400a device. when this pin is driven high, the device operates in the word (16 bit) mode. the data is read and programmed at dq0?q15. when this pin is driven low, the de- vice operates in byte (8 bit) mode. under this mode, the dq15/a-1 pin becomes the lowest address bit and dq8?q14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq0?q7 and the dq8?q15 bits are ignored. refer to figures 14 and 15 for the timing diagram. data protection the am29f400a is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the mem- ory contents only occurs after successful completion of speci? multi-bus cycle command sequences. the device also incorporates several features to pre- vent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, the am29f400a locks out write cy- cles for v cc < v lko (see dc characteristics section for voltages). when v cc < v lko , the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. the am29f400a ignores all writes until v cc > v lko . the user must ensure that the control pins are in the correct logic state when v cc > v lko to prevent unin- tentional writes. write pulse ?litch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il ,ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = vil and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
am29f400at/am29f400ab 17 preliminary 5.0 v-only flash embedded algorithms figure 1. embedded programming algorithm start programming completed last address ? write program command sequence (see below) data poll device increment address ye s no 5555h/aah 2aaah/55h 5555h/a0h program address/program data program command sequence (address/command): 20380b-8
18 am29f400at/am29f400ab preliminary embedded algorithms note: to insure the command has been accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 were high on the second status check, the command may not have been accepted. figure 2. embedded erase algorithm start erasure completed write erase command sequence (see below) data polling or toggle bit successfully completed 5555h/aah 2aaah/55h 5555h/80h chip erase command sequence (address/command): 5555h/aah 2aaah/55h 5555h/10h 5555h/aah 2aaah/55h 5555h/80h individual sector/multiple sector erase command sequence (address/command): 5555h/aah sector address/30h sector address/30h sector address/30h 2aaah/55h additional sector erase commands are optional 20380b-9
am29f400at/am29f400ab 19 preliminary 5.0 v-only flash figure 3. data polling algorithm start fail no dq7=data ? no pass ye s no ye s note: dq7 is rechecked even if dq5 = ? because dq7 may change simultaneously with dq5. dq7=data ? dq5=1 ? ye s read byte (dq0-dq7) addr=va read byte (dq0-dq7) addr=va va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = valid address equals any non-protected sector group address during chip erase 20380b-10
20 am29f400at/am29f400ab preliminary figure 4. toggle bit algorithm figure 5. maximum negative overshoot waveform figure 6. maximum positive overshoot waveform start fail no dq6=toggle ? no pass ye s no ye s note: dq6 is rechecked even if dq5 = ? because dq6 may stop toggling at the same time as dq5 changing to ?? dq6=toggle ? dq5=1 ? ye s read byte (dq0?q7) addr=don? care read byte (dq0?q7) addr=don? care 20380b-11 20 ns 20 ns +0.8 v -0.5 v 20 ns -2.0 v 20380b-12 20 ns v cc + 0.5 v 2.0 v 20 ns 20 ns v cc + 2.0 v 20380b-13
am29f400at/am29f400ab 21 preliminary 5.0 v-only flash absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . -65 c to +125 c ambient temperature with power applied. . . . . . . . . . . . . . -55 c to +125 c voltage with respect to ground all pins except a9, oe and reset (note 1) . . . . . . . . . . . . . . . . . . . . . . . -2.0 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . . -2.0 v to +7.0 v a9 , oe , and reset (note 2). . . . . . -2.0 v to +13.0 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to -2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 7 and figure 8. 2. minimum dc input voltage on pins a9, oe , and reset is -0.5 v. during voltage transitions, a9, oe , and reset may undershoot v ss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. see figure 7 and figure 8. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0?c to +70?c industrial (i) devices ambient temperature (t a ). . . . . . . . . . -40?c to +85?c extended (e) devices ambient temperature (t a ). . . . . . . . . -55?c to +125?c v cc supply voltages v cc for am29f400t/b-65, . . . . . . +4.75 v to +5.25 v v cc for am29f400t/b-70, -90, -120, -150 . . . . . . . . . . . . . . . . . . . +4.50 v to +5.50 v operating ranges define those limits between which the func- tionality of the device is guaranteed.
22 am29f400at/am29f400ab preliminary dc characteristics ttl/nmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded program or erase algorithm is in progress. 3. not 100% tested. parameter symbol parameter description test conditions min max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9, oe , reset input load current v cc = v cc max, a9, oe , reset = 12.5 v 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active read current (note 1) ce = v il , oe = v ih byte 40 ma word 50 i cc2 v cc active program/erase current (notes 2, 3) ce = v il , oe = v ih 60 ma i cc3 v cc standby current v cc = v cc max, ce = v ih , oe = v ih 1.0 ma v il input low voltage ?.5 0.8 v v ih input high voltage 2.0 v cc + 0.5 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh output high voltage i oh = -2.5 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage 3.2 4.2 v
am29f400at/am29f400ab 23 preliminary 5.0 v-only flash dc characteristics (continued) cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the frequency component typically is less than 2 ma/mhz, with oe at v ih . 2. i cc active while embedded program or erase algorithm is in progress. 3. not 100% tested. 4. i cc3 = 20 m a max at extended temperatures (> +85 c). parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 m a i lit a9, oe , reset input load current v cc = v cc max, a9, oe , reset = 12.5 v 50 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 m a i cc1 v cc active read current (note 1) ce = v il , oe = v ih byte 20 40 ma word 28 50 i cc2 v cc active program/erase current (notes 2, 3) ce = v il , oe = v ih 30 50 ma i cc3 v cc standby current (note 4) v cc = v cc max, ce = v ih , oe = v ih 15 m a v il input low voltage -0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 5.0 v 11.5 12.5 v v ol output low voltage i ol = 5.8 ma, v cc = v cc min 0.45 v v oh1 output low voltage i oh = ?.5 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?00 m a, v cc = v cc min v cc -0.4 v v lko low v cc lock-out voltage 3.2 4.2 v
24 am29f400at/am29f400ab preliminary ac characteristics read-only operations characteristics notes: parameter symbols speed option (notes 1 and 2) jedec standard description test setup -65 -70 -90 -120 -150 unit t avav t rc read cycle time (note 4) min 60 70 90 120 150 ns t avqv t acc address to output delay ce = v il oe = v il max 60 70 90 120 150 ns t elqv t ce chip enable to output delay oe = v il max 60 70 90 120 150 ns t glqv t oe output enable to output delay max 30 30 35 50 55 ns t ehqz t df chip enable to output high z (notes 3, 4) max 20 20 20 30 35 ns t ghqz t df output enable to output high z (notes 3, 4) max 20 20 20 30 35 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min00000ns t ready reset pin low to read mode (note 4) max 20 20 20 20 20 m s t elfl t elfh ce to byte switching low or high max55555ns 1. test conditions (for -65 only) output load: 1 ttl gate and 30 pf input rise and fall times: 5 ns input pulse levels:0.0 v to 3.0 v timing measurement reference level: 1.5 v input and output 2. test conditions (for -70, -90, -120, -150) output load: 1 ttl gate and 100 pf input rise and fall times: 20 ns input pulse levels: 0.45 v to 2.4 v timing measurement reference level: 0.8 v and 2.0 v input and output 3. output driver disable time 4. not 100% tested. 2.7 k w in3064 or equivalent c l 6.2 k w 5.0 v in3064 or equivalent device under test in3064 or equivalent in3064 or equivalent notes: for -65: c l = 30 pf including jig capacitance for all others: c l = 100 pf including jig capacitance 20380b-14 figure 7. test conditions
am29f400at/am29f400ab 25 preliminary 5.0 v-only flash ac characteristics write (erase/program) operations notes: 1. this does not include the preprogramming time. 2. not 100% tested. 3. these timings are for temporary sector unprotect operation. 4. output driver disable time. parameter symbols description speed option (notes 1 and 2) jedec standard -65 -70 -90 -120 -150 unit t avav t wc write cycle time min 60 70 90 120 150 ns t avwl t as address setup time min 00000ns t wlax t ah address hold time min 45 45 45 50 150 ns t dvwh t ds data setup time min 30 30 45 50 50 ns t whdx t dh data hold time min 00000ns t oeh output enable hold time read (note 2) min 00000ns toggle and data polling (note 2) min 10 10 10 10 10 ns t ghwl t ghwl read recovery time before write (oe high to we low) min00000ns t elwl t cs ce setup time min 00000ns t wheh t ch ce hold time min 00000ns t wlwh t wp write pulse width min 35 35 45 50 50 ns t whdl t wph write pulse width high min 20 20 20 20 20 ns t whwh1 t whwh1 programming operation byte typ 77777 m s word typ1414141414 m s t whwh2 t whwh2 sector erase operation (note 1) typ 1.0 1.0 1.0 1.0 1.0 sec max88888sec t vcs v cc setup time (note 2) min 50 50 50 50 50 m s t vidr rise time to v id (notes 2, 3) min 500 500 500 500 500 ns t oesp oe setup time to we active (notes 2, 3) min44444 m s t rp reset pulse width min 500 500 500 500 500 ns t flqz byte switching low to output high z (notes 3, 4) max 20 20 30 30 30 ns t busy program/erase valid to ry/by delay (note 2) min 30 30 35 50 55 ns t ressp reset setup time to we active min 44444 m s
26 am29f400at/am29f400ab preliminary key to switching waveforms switching waveforms figure 8. ac waveforms for read operations must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010 addresses ce oe we outputs addresses stable high z high z (t df ) (t oh ) output valid 20380b-15 t acc t oeh t oe (t ce ) t rc
am29f400at/am29f400ab 27 preliminary 5.0 v-only flash switching waveforms notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for the x16 mode. figure 9. program operation timings notes: 1. sa is the sector address for sector erase. addresses = don? care for chip erase. 2. these waveforms are for the x16 mode. figure 10. ac waveforms chip/sector erase operations d out pd t ah data polling t df t oh t oe t ds t cs t wph t dh t wp t ghwl addresses ce oe we data 5.0 v dq7 5555h pa a0h pa 3rd bus cycle 20380b-16 t wc t rc t as t whwh1 t ce t as t wp t cs t dh 5555h 2aaah sa ce oe we data v cc aah 55h addresses 2aaah t vcs t ds 5555h 5555h t wph t ghwl t ah aah 55h 80h 10h/30h 20380b-17
28 am29f400at/am29f400ab preliminary switching waveforms note: *dq7=valid data (the device has completed the embedded operation). figure 11. ac waveforms for data polling during embedded algorithm operations note: *dq6 stops toggling (the device has completed the embedded operation). figure 12. ac waveforms for toggle bit during embedded algorithm operations dq0-dq6 valid data t oe dq7= valid data high z ce oe we dq7 dq7 dq0-dq6 dq0-dq6=invalid * 20380b-18 t oeh t ce t ch t df t oh t whwh 1 or 2 ce t oeh we oe dq6= stop toggling dq0-dq7 valid dq6=toggle dq6=toggle data (dq0-dq7) * t oe 20380b-19
am29f400at/am29f400ab 29 preliminary 5.0 v-only flash switching waveforms figure 13. ry/by timing diagram during program/erase operations figure 14. reset timing diagram ce we ry/by t busy entire programming or erase operations the rising edge of the last we signal 20380b-20 reset 20380b-21 t ready t rp
30 am29f400at/am29f400ab preliminary switching waveforms figure 15. byte timing diagram for read operation figure 16. byte timing diagram for write operations ce oe byte t elfl t elfh dq0-dq14 data output (dq0-dq14) data output (dq0-dq7) dq15/a-1 dq15 output address input 20380b-22 t flqz ce we byte the falling edge of the last we signal t hold (t ah ) t set (t as ) 20380b-23
am29f400at/am29f400ab 31 preliminary 5.0 v-only flash notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. figure 17. temporary sector unprotect algorithm figure 18. temporary sector unprotect timing diagram start perform erase or program operations reset = v ih temporary sector group unprotect completed (note 2) reset = v id (note 1) 20380b-24 ry/by program or erase command sequence 20380b-25 reset ce we 5 v 12 v t vidr
32 am29f400at/am29f400ab preliminary ac characteristics write/erase/program operations alternate ce controlled writes notes: 1. this does not include the preprogramming time. 2. not 100% tested. parameter symbols description speed option (notes 1 and 2) unit jedec standard -65 -70 -90 -120 -150 t avav t wc write cycle time (note 2) min 60 70 90 120 150 ns t avel t as address setup time min 00000ns t elax t ah address hold time min 45 45 45 50 50 ns t dveh t ds data setup time min 30 30 45 50 50 ns t ehdx t dh data hold time min 00000ns t oes output enable setup time min 00000ns t oeh output enable hold time read (note 2) min 00000ns toggle and data polling (note 2) min 10 10 10 10 10 ns t ghel t ghel read recover time before write min 00000ns t wlel t ws we setup time min 00000ns t ehwh t wh we hold time min 00000ns t eleh t cp ce pulse width min 35 35 45 50 50 ns t ehel t cph ce pulse width high min 20 20 20 20 20 ns t whwh1 t whwh1 programming operation byte typ 77777 m s word typ1414141414 m s t whwh2 t whwh2 sector erase operation (note 1) typ 1.0 1.0 1.0 1.0 1.0 sec max88888sec t flqz byte switching low to output high z (note 2) max 20 20 30 30 30 ns
am29f400at/am29f400ab 33 preliminary 5.0 v-only flash switching waveforms notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. 6. these waveforms are for the x16 mode. figure 19. alternate ce controlled program operation timings erase and programming performance notes: 1. 25 c, 5.0 v v cc , 100,000 cycles. 2. although embedded algorithms allow for longer chip program and erase time, the actual time will be considerably less since bytes program or erase signi?antly faster than the worst case byte. 3. under worst case condition of 90 c, 4.5 v v cc , 100,000 cycles. 4. system-level overhead is de?ed as the time required to execute the four bus cycle command necessary to program each byte. in the preprogramming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. the embedded algorithms allow for 2.5 ms byte program time. dq5 = ? only after a byte takes the theoretical maximum time to program. a minimal number of bytes may require signi?antly more programming pulses than the typical byte. the majority of the bytes will program within one or two pulses. this is demonstrated by the typical and maximum programming times listed above. parameter limits unit comments typ (note 1) max sector erase time 1.0 8 sec excludes 00h programming prior to erasure chip erase time 11 88 sec excludes 00h programming prior to erasure byte programming time 7 300 (note 3) m s excludes system-level overhead (note 4) word programming time 14 600 m s excludes system-level overhead (note 4) chip programming time 3.6 10.8 (notes 3, 5) sec excludes system-level overhead (note 4) d out pd t ah data polling t ds t ws t cph t dh t cp t ghel addresses we oe ce data 5.0 volt dq7 5555h pa a0h pa 20380b-26 t wc t as t whwh1
34 am29f400at/am29f400ab preliminary latchup characteristics includes all pins except v cc . test conditions: v cc = 5.0 v, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. so pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. data retention min max input voltage with respect to v ss on all i/o pins ?.0 v v cc + 1.0 v v cc current ?00 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v pp = 0 8 10 pf parameter test conditions min unit minimum pattern data retention time 150 c 10 years 125 c 20 years
am29f400at/am29f400ab 35 preliminary 5.0 v-only flash revision summary distinctive characteristics: high performance: the fastest speed option available is now 60 ns. enhanced power management for standby mode: changed typical standby current to 1 m a. general description: first paragraph, ?st sentence should read, ?..orga- nized as 512 kbytes of 8 bits each or 256 kwords of 16 bits each. added 60 ns speed option. product selector guide: added -65 column (60 ns, 5% v cc ). added -70 (70 ns, 10% v cc ) and deleted -75 speed option. ordering information, standard products: the -65 speed option is now listed in the example. valid combinations: added -65 and -70, and deleted - 75 speed options. tables 1 and 2, user bus operations: corrected we for read operations; was don? care (x), is now h. standby mode: corrected standby mode current; was 100 m a, is now 5 m a. table 5, sector address tables (am29f400ab): corrected x16 starting address for sa5; was 1c000h, is now 28000h. erase suspend: third paragraph, third sentence: deleted the word ?ot. operating ranges: v cc supply voltages: added -65 and deleted -75 speed options in the list. changed a9 maximum to +13.0 v. dc characteristics: cmos compatible: revised i cc speci?ations. added note 4 (refers to i cc3 ). ac characteristics: read only operations characteristics: added the -65 column and test conditions. replaced -75 column with -70 column. test conditions, figure 7: changed speed option in ?st c l statement from -75 to -65. ac characteristics: write/erase/program operations, alternate ce con- trolled writes: added the -65 column. replaced -75 column with -70 column. revised sector erase and programming speci?ations. erase and programming performance: revised speci?ations in table. clari?d table and notes. table 7, command de?itions revised note 5 to cover all upper address bits that are don? care. deleted note 6.

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